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L6387E High-voltage high and low side driver Features High voltage rail up to 600V dV/dt immunity 50V/nsec in full temperature range Driver current capability: - 400mA source, - 650mA sink Switching times 50/30 nsec rise/fall with 1nF load CMOS/TTL Schmitt trigger inputs with hysteresis and pull down Internal bootstrap diode Outputs in phase with inputs Interlocking function DIP-8 SO-8 Description The L6387E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The high side (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. Figure 1. Block diagram BOOTSTRAP DRIVER 8 Vboot H.V. Cboot VCC 3 UV DETECTION R HVG DRIVER S VCC 7 HVG HIN 2 LOGIC LEVEL SHIFTER OUT 6 5 LVG DRIVER LVG TO LOAD LIN 1 4 GND D00IN1135 October 2007 Rev 1 1/15 www.st.com 15 Contents L6387E Contents 1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 3.2 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 7 8 9 Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/15 L6387E Electrical data 1 1.1 Electrical data Absolute maximum ratings Table 1. Symbol Vout Vcc Vboot Vhvg Vlvg Vi dVout/dt Ptot Tj Ts Output voltage Supply voltage Floating supply voltage High side gate output voltage Low side gate output voltage Logic input voltage Allowed output slew rate Total power dissipation (TJ = 85 C) Junction temperature Storage temperature Absolute maximum ratings Parameter Value -3 to Vboot -18 - 0.3 to +18 -1 to 618 -1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V V V V V V/ns mW C C Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model) 1.2 Thermal data Table 2. Symbol Rth(JA) Thermal data Parameter Thermal Resistance Junction to ambient SO-8 150 DIP-8 100 Unit C/W 1.3 Recommended operating conditions Table 3. Symbol Vout VBS (2) Recommended operating conditions Pin 6 8 Parameter Output voltage Floating supply voltage Switching frequency 3 Supply voltage Junction temperature -45 HVG,LVG load CL = 1nF Test condition Min (1) (1) Typ Max 580 17 400 17 125 Unit V V kHz V C fsw Vcc TJ 1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V 2. VBS = Vboot - Vout 3/15 Pin connection L6387E 2 Pin connection Figure 2. Pin connection (Top view) LIN HIN VCC GND 1 2 3 4 D97IN517A 8 7 6 5 Vboot HVG OUT LVG Table 4. N 1 2 3 4 5 6 7 8 Pin description Pin LIN HIN Vcc GND LVG (1) VOUT HVG (1) Vboot O O O Type I I Low side driver logic input High side driver logic input Low voltage power supply Ground Low side driver output High side driver floating reference High side driver output Bootstrap supply voltage Function 1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. 4/15 L6387E Electrical characteristics 3 3.1 Electrical characteristics AC operation Table 5. Symbol ton toff tr tf AC operation electrical characteristcs (VCC = 15V; TJ = 25C) Pin Parameter Test condition Vout = 0V Vout = 0V CL = 1000pF CL = 1000pF Min Typ 110 105 50 30 Max Unit ns ns ns ns 1 vs 5 High/low side driver turn-on 2 vs 7 propagation delay 1 vs 5 High/low side driver turn-off 2 vs 7 propagation delay 5, 7 5, 7 Rise time Fall time 3.2 DC operation Table 6. Symbol DC operation electrical characteristcs (VCC = 15V; TJ = 25C) Pin Parameter Test condition Min Typ Max Unit Low supply voltage section Vcc Vccth1 Vccth2 Vcchys 3 Iqccu Iqcc Rdson Supply voltage Vcc UV turn on threshold Vcc UV turn off threshold Vcc UV hysteresis Undervoltage quiescent supply current Quiescent current Bootstrap driver on resistance(1) Vcc 9V Vcc = 15V Vcc 12.5V 5.5 5 6 5.5 0.5 150 250 125 220 320 17 6.5 6 V V V V A A Bootstrapped supply voltage section VBS IQBS ILK 8 Bootstrap supply voltage VBS quiescent current High voltage leakage current HVG ON Vhvg = Vout = Vboot = 600V 17 100 10 V A A High/low side driver Iso Isi Source short circuit current 5,7 Sink short circuit current VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) 300 450 400 650 mA mA 5/15 Input logic Table 6. Symbol L6387E DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25C) Pin Parameter Test condition Min Typ Max Unit Logic inputs Vil Vih Iih Iil 1,2 Low level logic threshold voltage High level logic threshold voltage High level logic input current Low level logic input current VIN = 15V VIN = 0V 3.6 50 70 1 1.5 V V mA mA 1. RDS(on) is tested in the following way: ( V CC - V CBOOT1 ) - ( V CC - V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) - I 2 ( V CC ,V CBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2 4 Input logic L6387E Input Logic is VCC (17V) compatible. An interlocking features is offered (see truth table below) to avoid undesired simultaneous turn ON of both Power Switches driven. Table 7. Input LIN HVG Output LVG 0 1 0 0 0 0 1 0 0 1 1 0 Input logic HIN 0 0 1 1 6/15 L6387E Bootstrap driver 5 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 3 a). In the L6387E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 3 b. An internal charge pump (Figure 3 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 5.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. 7/15 Bootstrap driver L6387E For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact: 30nC V drop = -------------- 125 0.8V 5s Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 3. Bootstrap driver DBOOT VS VBOOT H.V. HVG CBOOT VOUT TO LOAD LVG a VBOOT H.V. HVG VS CBOOT VOUT TO LOAD LVG b D99IN1056 8/15 L6387E Typical characteristic 6 Typical characteristic Figure 4. time (nsec) 250 200 Tr 150 Tf 100 50 0 Typical rise and fall times vs load capacitance D99IN1054 Figure 5. Iq (A) 104 Quiescent current vs supply voltage D99IN1055 103 102 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb 0 2 4 6 8 10 12 14 16 VS(V) Figure 6. 250 Turn on time vs temperature @ Vcc = 15V Figure 7. 250 Turn Off time vs temperature @ Vcc = 15V 200 200 Toff (ns) 150 100 50 0 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. Ton (ns) 150 100 50 0 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. Figure 8. 1000 Output source current vs temperature @ Vcc = 15V Figure 9. 1000 Output sink current vs temperature @ Vcc = 15V 800 800 current (mA) 600 400 200 0 Typ. current (mA) 600 Typ. 400 200 0 -45 -25 0 25 50 Tj (C) 75 100 125 -45 -25 0 25 50 Tj (C) 75 100 125 9/15 Package mechanical data L6387E 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 10/15 L6387E Package mechanical data Figure 10. DIP-8 mechanical data and package dimensions mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch OUTLINE AND MECHANICAL DATA DIP-8 11/15 Package mechanical data Figure 11. SO-8 mechanical data and package dimensions mm DIM. MIN. A A1 A2 b c D (1) L6387E inch MAX. 1.750 MIN. TYP. MAX. 0.0689 0.0098 TYP. OUTLINE AND MECHANICAL DATA 0.100 1.250 0.280 0.170 4.800 5.800 3.800 4.900 6.000 3.900 1.270 0.250 0.400 1.040 0 0.250 0.0039 0.0492 0.480 0.0110 0.230 0.0067 0.0189 0.0091 5.000 0.1890 0.1929 0.1969 6.200 0.2283 0.2362 0.2441 4.000 0.1496 0.1535 0.1575 0.0500 0.500 0.0098 1.270 0.0157 0.0409 8 0.100 0 8 0.0039 0.0197 0.0500 E E1 (2) e h L L1 k ccc Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. SO-8 0016023 D 12/15 L6387E Order codes 8 Order codes Table 8. Order codes Part number L6387E L6387ED L6387ED013TR Package DIP-8 SO-8 SO-8 Packaging Tube Tube Tape and reel 13/15 Revision history L6387E 9 Revision history Table 9. Date 11-Oct-2007 Document revision history Revision 1 First release Changes 14/15 L6387E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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